The present disclosure relates to a nonvolatile memory devices, memory systems (including memory cards) incorporating same, and methods of programming nonvolatile memory devices. More particularly, the disclosure relates to methods of operating a nonvolatile memory device and/or memory system that provide an ability to dynamically select between different verification modes used during the programming of nonvolatile memory cells.
Nonvolatile memory and related memory systems have become design mainstays within contemporary consumer electronics and digital data systems. Nonvolatile memory allows a large volume of data to be stored by a relatively small integrated circuit device that may be reliably operated with low power consumption, and yet may afford relatively fast data access. Unlike volatile forms of memory (e.g., DRAM and SRAM), nonvolatile memory is able to retain stored data in the absence of applied power.
There are different types of nonvolatile memory. One widely used type is the Electrically Erasable and Programmable Read Only Memory (EEPROM). EEPROM comes in different forms including the various types of flash memory.
In early forms, the individual nonvolatile memory cells stored only a single bit of binary data (“1” or “0”). Such memory cells are referred to a single level memory cells (SLC) and are still widely used. However, many contemporary nonvolatile memory cells are able to store 2 or more bits of data, and are generally referred to as multi-level memory cells (MLC). MLCs offer increased data integration density, but do so at the price of increasingly complex methods of operation (e.g., programming, reading, and erase operations).
The threshold voltage exhibited by a MLC must be accurately programmed within a desired (or “target”) threshold voltage distribution. The voltage range of the threshold voltage distribution indicates a corresponding data state for the programmed MLC.
As the number of valid MLC data states increases (e.g., four (4) states for a 2-bit MLC, and eight (8) states for a 3-bit MLC, etc.) so too does the number of corresponding threshold voltage distributions. This expanded number of data states and corresponding threshold voltage distributions presents a number of challenges to contemporary nonvolatile memory designers. One particular challenge is managing the design and operating trade-offs between programming speed and programming accuracy. Another challenge is managing the useful life of nonvolatile memory cells in view of the great multiplicity of applied programming and erase operations.